Jinming Zhuang

Jinming Zhuang

Ph.D. Student

Brown University

Biography

Welcome to Jinming Zhuang’s (庄谨铭) Homepage! Jinming is a fourth-year Ph.D. student in ECE department at Brown University, supervised by Prof. Peipei Zhou. He received his B.E. degree in Electronic Engineering from University of Electronic Science and Technology of China(UESTC) in 2021. His research interest lies in Heterogeneous Computing, Compiler Design & Programming Abstraction for Accelerators, HW/SW Co-design, and Domain-Specific Accelerator Design. His works have received the 2025 ACM/SIGDA FPGA Best Paper Nominee, 2024 IEEE IGSC Best Viewpoint Paper, and 2021 ACM/IEEE DAC Young Student Fellow Best Video Award.

Recently, our work “ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines” (2025 FPGA Best Paper Nominee)has been open-sourced on GitHub: https://github.com/arc-research-lab/Aries.

Feel free to reach out to me for any discussions, and welcome to use all of our open-source tools!

Interests
  • Heterogeneous Computing: FPGAs, GPUs, ASICs and NPUs
  • Compiler Design & Programming Abstraction
  • Hardware & Software Co-design
Education
  • PhD in Electrical and Computer Engineering, 2024 - Present

    Brown University

  • PhD in Electrical and Computer Engineering, 2021 - 2024

    University of Pittsburgh

  • BSc in Electronic Science and Engineering, 2017 - 2021

    University of Electronic Science and Technology of China (UESTC)

Publications

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(2025). ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines(FPGA 2025 Best Paper Candidate). Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025, Feb. 28 - March 3, Monterey, CA, US. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3706628.3708870.

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(2024). Amortizing Embodied Carbon Across Generations (Best Viewpoint Paper in IGSC 2024). Proceedings of the IEEE 15th International Green and Sustainable Computing Conference, IGSC 2024.

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(2024). EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) in conjunction with (ESWEEK), RALEIGH, NC, USA, Sept. 29-Oct. 4, 2024. Also appears as part of the ESWEEK-TCAD Special Issue, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

Slides

(2024). CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. ACM Transactions on Reconfigurable Technology and Systems.

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(2024). SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, March 3 - March 5, Monterey, CA, US. Full Paper Accepted! https://doi.org/10.1145/3626202.3637569.

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