Jinming Zhuang

Jinming Zhuang

Assistant Professor of Kate Gleason College of Engineering

Rochester Institute of Technology

Biography

Dr. Jinming Zhuang (庄谨铭) is a tenure-track Assistant Professor in the Department of Computer Engineering at the Rochester Institute of Technology. He received his B.E. in Electronic Engineering from the University of Electronic Science and Technology of China (UESTC) in 2021 and completed his Ph.D. in the School of Engineering at Brown University in 2026. His research interest lies in Heterogeneous Computing, Compiler Design & Programming Abstraction for Accelerators, HW/SW Co-design, and Domain-Specific Accelerator Design. His works have received the 2025 ACM/SIGDA FPGA Best Paper Nominee, 2024 IEEE IGSC Best Viewpoint Paper, and 2021 ACM/IEEE DAC Young Student Fellow Best Video Award.

Interests
  • Heterogeneous Computing: FPGAs, GPUs, ASICs and NPUs
  • Compiler Design & Programming Abstraction
  • AI Hardware & Software Co-design
Education

  • PhD in Electrical and Computer Engineering, 2024 - 2026

    Brown University, advised by Prof. Peipei Zhou

  • PhD in Electrical and Computer Engineering (Transferred), 2021 - 2024

    University of Pittsburgh, advised by Prof. Peipei Zhou

  • BSc in Electronic Science and Engineering, 2017 - 2021

    University of Electronic Science and Technology of China (UESTC)

Recent News

All news»

  • [2026/04] Exciting news: I will be joining the Computer Engineering Department at the Rochester Institute of Technology (RIT) as a tenure-track Assistant Professor starting Fall 2026.

Publications

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Erwei Wang, Samuel Bayliss, Andra Bisca, Zachary Blair, Sangeeta Chowdhary, Kristof Denolf, Jeff Fifield, Brandon Freiberger, Erika Hunhoff, Phil James-Roxby, Jack Lo, Joseph Melber, Stephen Neuendorffer, Eddie Richter, André Rosti, Javier Setoain, Gagandeep Singh, Endri Taka, Pranathi Vasireddy, Zhewen Yu, Niansong Zhang, Jinming Zhuang (2026). From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2026. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3785670.

Cite PDF Code

Zhuoping Yang, Jinming Zhuang, Xingzhen Chen, Alex Jones, Peipei Zhou (2025). AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2025, Nov. 16 - Nov. 21, 2025, St. Louis, MO, US. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3712285.3759778.

Cite PDF Code Video

Jinming Zhuang, Shaojie Xiang*, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou (2025). ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025 Best Paper Candidate, Feb. 28 - March 3, Monterey, CA, US. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3706628.3708870.

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Shixin Ji, Jinming Zhuang, Zhuoping Yang, Alex Jones, Peipei Zhou (2024). Amortizing Embodied Carbon Across Generations (Best Viewpoint Paper in IGSC 2024). Proceedings of the IEEE 15th International Green and Sustainable Computing Conference, IGSC 2024.

Cite Slides IEEE

Peiyan Dong*, Jinming Zhuang* (co-first author), Zhuoping Yang, Shixin Ji, Yanyu Li, Dongkuan Xu, Heng Huang, Jingtong Hu, Alex Jones, Yiyu Shi, Yanzhi Wang, Peipei Zhou (2024). EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) in conjunction with (ESWEEK), RALEIGH, NC, USA, Sept. 29-Oct. 4, 2024. Also appears as part of the ESWEEK-TCAD Special Issue, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

Slides

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Experience

 
 
 
 
 
Rochester Institute of Technology
Tenure-Track Assistant Professor
Rochester Institute of Technology
Aug 2024 – Present Rochester, NY
  • Department of Computer Engineering, Kate Gleason College of Engineering.
  • Research focusing on hetergeneous computing, hardware abstractions, and compiler optimizations for AI systems.
 
 
 
 
 
AMD (RAD Team)
Hardware & Compiler Engineer Intern
AMD (RAD Team)
May 2022 – Aug 2022 Longmont, CO
  • Contributed to MLIR-AIE and MLIR-AIR projects, developing hardware abstractions and compilation flows for AMD Ryzen AI NPUs.
  • Work culminated in peer-reviewed publications at FPGA ‘23 (CHARM) and ACM TRETS ‘26 (MLIR-AIR).