Jinming Zhuang

Jinming Zhuang

Assistant Professor of Kate Gleason College of Engineering

Rochester Institute of Technology

Biography

Jinming Zhuang is a tenure-track Assistant Professor in the Department of Computer Engineering at the Rochester Institute of Technology. He received his B.Eng. from the University of Electronic Science and Technology of China (UESTC) in 2021 and completed his Ph.D. at Brown University in 2026 supervised by Professor Peipei Zhou. His research interests lie in Heterogeneous Computing, Compiler Design & Programming Abstraction for Accelerators, and AI HW/SW Co-design. His works have received the 2025 ACM/SIGDA FPGA Best Paper Nominee, 2024 IEEE IGSC Best Viewpoint Paper, and 2021 ACM/IEEE DAC Young Student Fellow Best Video Award.

Actively Recruiting Students: I have fully funded Ph.D. positions available for self-motivated students starting in Spring/Fall 2027 who are interested in hardware accelerators (FPGAs, GPUs, NPUs) and AI compilers. If you are interested in joining my group, please contact me with your CV at jxzeec at rit.edu.
Interests
  • Heterogeneous Computing: FPGAs, GPUs, and NPUs
  • Compiler Design & Programming Abstraction
  • AI Hardware & Software Co-design
Education
  • Ph.D. in Electrical and Computer Engineering, 2024 - 2026

    Brown University, advised by Prof. Peipei Zhou

  • Ph.D. in Electrical and Computer Engineering (Transferred), 2021 - 2024

    University of Pittsburgh, advised by Prof. Peipei Zhou

  • B.Eng. in Electronic Science and Engineering, 2017 - 2021

    University of Electronic Science and Technology of China (UESTC)

To Prospective Students

Earning a Ph.D. is a challenging pursuit of learning, exploration, and discovery. I value self-motivated students who are genuinely curious about their research and excited by its potential impact. Below are several intriguing questions. If you can envision yourself enjoying exploring and tackling problems in these areas, our group may be a good fit.

  • Architecture: How can we tackle the memory wall through better data orchestration within and across devices by identifying and leveraging the key features of FPGAs, GPUs, CPUs, and emerging hardware?
  • Compiler: How can AI models defined in PyTorch be automatically lowered to heterogeneous systems with formally verified correctness and high hardware efficiency?
  • HW/SW Co-design: From a hardware perspective, what will future AI models look like (numerical data types, customized structures, etc.) to achieve lower latency and better energy efficiency?

Most of my work is open-source, providing accessible starting points for learning and further exploration. I provide hands-on support and side-by-side guidance while encouraging students to explore and develop their own research ideas.

Recent News

All news»

  • [2026/08] New chatper starts at RIT!

  • [2026/04] Two full papers are accepted at ACM GLSVLSI 2026, DORA and μ-ORCA.

  • [2026/04] I will be joining the Computer Engineering Department at the Rochester Institute of Technology (RIT) as a tenure-track Assistant Professor starting Fall 2026.

  • [2026/03] Two full papers are accepted at ACM/IEEE DAC 2026. FILCO and PHAROS.

Publications

(2026). From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2026. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3785670.

Cite PDF Code

(2025). AGILE: Lightweight and Efficient Asynchronous GPU-SSD Integration. Proceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2025, Nov. 16 - Nov. 21, 2025, St. Louis, MO, US. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3712285.3759778.

Cite PDF Code Video

(2025). ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025 Best Paper Candidate, Feb. 28 - March 3, Monterey, CA, US. Full Paper Accepted! https://dl.acm.org/doi/10.1145/3706628.3708870.

Cite PDF Code

(2024). Amortizing Embodied Carbon Across Generations (Best Viewpoint Paper in IGSC 2024). Proceedings of the IEEE 15th International Green and Sustainable Computing Conference, IGSC 2024.

Cite Slides IEEE

(2024). EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) in conjunction with (ESWEEK), RALEIGH, NC, USA, Sept. 29-Oct. 4, 2024. Also appears as part of the ESWEEK-TCAD Special Issue, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

Slides

Experience

 
 
 
 
 
Rochester Institute of Technology
Tenure-Track Assistant Professor
Aug 2024 – Present Rochester, NY
  • Department of Computer Engineering, Kate Gleason College of Engineering.
  • Research focusing on hetergeneous computing, hardware abstractions, and compiler optimizations for AI systems.
 
 
 
 
 
AMD (RAD Team)
Hardware & Compiler Engineer Intern
May 2022 – Aug 2022 Longmont, CO
  • Contributed to MLIR-AIE and MLIR-AIR projects, developing hardware abstractions and compilation flows for AMD Ryzen AI NPUs.
  • Work culminated in peer-reviewed publications at FPGA ‘23 (CHARM) and ACM TRETS ‘26 (MLIR-AIR).