ARIES Project

Overview

ARIES is an agile MLIR-based compilation flow for reconfigurable devices with AMD AI Engines. ARIES takes as input the user programs defined by our Python programming interface. The IR builder will parse the Python abstract syntax tree and generate the ARIES initial IR. Then our MLIR-Based unified middle end performs the global and local optimizations to transform the initial IR to the ARIES final IR before code generation. We implement translation and conversion passes within MLIR to target multiple backends such as AMD Versal and NPU heterogeneous devices. By increasing the abstraction level from RTL, C intrinsics to Python, ARIES greatly improves the programming productivity for heterogeneous architectures.

Existing Key Features of ARIES

• Unified programming interface in Python targeting heterogeneous architectures with CPUs, FPGAs, and AMD AI Engine (AIE) NPUs.

• Simplified abstraction exposing off-chip memory, AIE local scratchpad memory, and AIE compute tiles while abstracting hardware details such as AIE placement and locks to improve programming productivity.

• MLIR-based compilation flow automatically lowering programs to AMD XRT for CPUs, HLS C/C++ for FPGAs, and ADF graphs for AIEs.

• Open-source infrastructure for research and further exploration.

Ongoing Optimizations

The memory wall remains a major challenge in modern computer architectures. Dataflow architectures alleviate expensive external memory accesses through on-chip FIFOs and buffers, but several key compiler and programming capabilities are still needed for FPGAs and AIEs:

• Scratchpad memory abstraction: A unified abstraction that properly exposes multi-level scratchpad memories—including AIE local/shared memory and FPGA BRAM/URAM—to enable better on-chip data reuse while reducing programming effort.

• AIE kernel compilation: General compiler passes for automatic vectorization and code generation are needed to compile arbitrary AIE kernels, enabling flexible kernel fusion without relying on predefined kernel templates.

Goal of Developing ARIES

• ARIES aims to raise the level of hardware abstraction, enabling domain experts to more easily leverage advanced heterogeneous hardware, including FPGAs from different vendors, AMD Ryzen AI NPUs, and AMD Versal ACAPs.

• ARIES will remain open-source and be continuously developed to support further research and exploration. It will also be integrated into Reconfigurable Computing courses at RIT to help train the next generation of researchers and engineers.

Publications

[3] ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2025 (FPGA'25 Best Paper Nominee).

[2] SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2024 (FPGA'24).

[1] CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2023 (FPGA'23).

Open Source

• ARIES: https://github.com/arc-research-lab/Aries (Over 65 stars since 2025)
• CHARM: https://github.com/arc-research-lab/CHARM (Over 175 stars since 2023)