1

ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines(FPGA 2025 Best Paper Candidate)
Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou
Cite PDF Code
ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines(FPGA 2025 Best Paper Candidate)
Amortizing Embodied Carbon Across Generations (Best Viewpoint Paper in IGSC 2024)
Shixin Ji, Jinming Zhuang, Zhuoping Yang, Alex Jones, Peipei Zhou
Cite Slides IEEE
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou
Cite PDF Code
Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
Zhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang, Weifeng Zhang, Dharmesh Jani, Peipei Zhou
Cite IEEE arXiv
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
Zhuoping Yang, Jinming Zhuang, Peipei Zhou
Cite Code
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives
Jinming Zhuang, Zhuoping Yang, Peipei Zhou
PDF Cite Code
High Performance, Low Power Matrix Multiply Design on ACAP: from Architecture, Design Challenges and DSE Perspectives
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture
Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou
PDF Cite Code
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture