FPGA

ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines(FPGA 2025 Best Paper Candidate)
Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou
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ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines(FPGA 2025 Best Paper Candidate)
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou
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