https://www.jinmingzhuang.com/tag/hbm/HBMWowchemy (https://wowchemy.com)en-usFri, 24 Jul 2026 00:00:00 +0000https://www.jinmingzhuang.com/media/icon_hud2108d851331ec1ab1d959c327988c6d_37739_512x512_fill_lanczos_center_3.pnghttps://www.jinmingzhuang.com/tag/hbm/https://www.jinmingzhuang.com/project/chiron/Fri, 24 Jul 2026 00:00:00 +0000https://www.jinmingzhuang.com/project/chiron/<div class="chiron-project"> <h2 id="overview">Overview</h2> <p>CHIRON is a polyhedral model-based MLIR compiler for spatial dataflow architectures. It provides an end-to-end flow from AI models defined in PyTorch to optimized heterogeneous accelerators, while formally verifying tiled dataflow execution and automatically exploring the design space for performance.</p> <p>CHIRON targets the memory wall by enabling intermediate data to be forwarded through on-chip buffers and interconnects rather than repeatedly accessing off-chip memory.</p> <h2 id="features-and-status-of-chiron">Features and Status of CHIRON</h2> <ul> <li> <p><strong>End-to-end compilation:</strong> Supports AI models defined in PyTorch and automatically lowers them to AMD VHK158 FPGAs with HBM and VCK190 devices with AI Engines (AIEs).</p> </li> <li> <p><strong>Correctness-guaranteed optimization:</strong> Integrates a polyhedral-based verifier for tiled dataflow correctness, buffer analysis, an accurate performance cost model, and automated design space exploration.</p> </li> <li> <p><strong>Performance:</strong> On-board evaluation on AMD VHK158 achieves <strong>1.93× higher GPT-2 FP32 decoding speed and 3.13× better energy efficiency</strong> than an NVIDIA A100 GPU, comparing device-side execution without host-to-device communication.</p> </li> <li> <p><strong>Status:</strong> CHIRON is currently under submission.</p> </li> </ul> <h2 id="key-infrastructure-for-the-community">Key Infrastructure for the Community</h2> <ul> <li> <p><strong>Compiler Infrastructure:</strong> An open-source end-to-end automated compilation framework from PyTorch to dataflow-enabled FPGAs and AMD Versal AIE devices, designed to be extensible across heterogeneous dataflow architectures.</p> </li> <li> <p><strong>Hardware Infrastructure:</strong> An open-source Vitis platform (<code>.xpfm</code>) for the Versal HBM series, with performance-tuned NoC connectivity and QoS supporting <strong>32 HBM pseudo-channels and 64 HBM NMUs</strong>, providing an Alveo-like platform for HBM-based accelerator design and research.</p> </li> </ul> <h2 id="ongoing-and-future-work">Ongoing and Future Work</h2> <ul> <li> <p><strong>Heterogeneous dataflow:</strong> Explore dataflow optimization across heterogeneous devices, such as using AIE-enabled devices for <strong>prefill</strong> and HBM-equipped devices for <strong>decoding</strong>.</p> </li> <li> <p><strong>Multi-device compilation:</strong> Automatically partition extremely large models across multiple devices to minimize inter-device communication while guaranteeing execution correctness.</p> </li> </ul> </div>